Calls for papers
![International Journal of High Performance Systems Architecture International Journal of High Performance Systems Architecture](https://www.inderscience.com/images/cover/scoverijhpsa.jpg)
International Journal of High Performance Systems Architecture
Special Issue on: "Embedded Multicore and Reconfigurable Architectures"
Guest Editor:
Dr. Chao Wang, University of Science and Technology of China, China
Reconfigurable and multicore architectures are promising solutions for embedded systems. Compared to conventional hardware with fixed functionalities, reconfigurable hardware has better flexibility in using limited hardware resources. Developers of embedded systems can also use the reconfigurable technology to satisfy system requirements such as constrained area, high performance and low power consumption.
In contrast, in conventional uniprocessor architecture, all loads of computation burden the only core and performance is limited to a critical section. This limitation has been solved by multicore architecture.
Since adopting both reconfigurability and multicore architectures can achieve high performance, how to inte-grate these two technologies to achieve much higher performance is an attractive research issue. The aim of this special issue is to encourage researchers to publish their cutting-edge experiences in reconfigurable computing technologies, multicore embedded systems, and the integration of the two research areas.
Subject CoverageSuitable topics include but are not limited to:
- Reconfigurable embedded systems
- Reconfigurable hardware architectures
- Runtime resource management of reconfigurable hardware
- Application design for reconfigurable embedded systems
- Dynamic partial reconfiguration techniques
- Programming models for reconfigurable systems (OpenCL, etc.)
- Multicore embedded systems track
- Multicore operating systems and scheduling
- Hardware and application design for multicore architectures
- Programming models for embedded multicore architectures
- Homogeneous and heterogeneous multicore architectures and applications (e.g. MapReduce, GPU CUDA or FPGA-based acceleration engines)
- Memory and cache sub-systems in multicore and reconfigurable computing
Notes for Prospective Authors
Submitted papers should not have been previously published nor be currently under consideration for publication elsewhere. (N.B. Conference papers may only be submitted if the paper was not originally copyrighted and if it has been completely re-written).
All papers are refereed through a peer review process. A guide for authors, sample copies and other relevant information for submitting papers are available on the Author Guidelines page.
Important Dates
Submission due: 10 October, 2012 (tentative)
First round acceptance: 1 November, 2012
Revisions due: 15 November, 2012
Final decision: 1 December, 2012
Final versions due by: 10 December, 2012
Note the deadlines for this special issue are tentative, as we seek around 5 to 6 papers meeting the technical scope and criteria. Authors are strongly encouraged to submit well-prepared manuscripts that are complete and ready for publication. Submitted articles will be processed immediately when they are in the online system. After enough papers are collected, other excellent papers will appear in regular issues of the journal.