Improved low power implicit pulse triggered flip-flop with reduced power dissipation
by G. Ravi; J.P. SenthilKumar; S. Vinothini Jane
International Journal of Computational Complexity and Intelligent Algorithms (IJCCIA), Vol. 1, No. 2, 2019

Abstract: In this paper, an improved implicit pulse triggered flip-flop is proposed based on conditional pulse enhancement scheme. The pass transistor logic AND gate creates a faster discharge path. Then a conditional pulse enhancement scheme is used in order to conditionally enhance the pulse only when required. This avoids unnecessary switching action in the flip-flop. Then in order to reduce the power dissipation further, the pseudo NMOS logic is replaced with a NAND gate structure. This reduces the static power consumption and as well as the switching power consumption. Thus results in an overall power saving. The results are obtained in 180 nm CMOS technology using mentor graphics. The results are compared with four conventional flip-flops and its power saving is improved.

Online publication date: Tue, 26-Nov-2019

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