VLSI implementation of an efficient MBIST architecture using RLFSR Online publication date: Wed, 19-Aug-2020
by Omanakuttan Sheela Nisha; K. Siva Sankar
International Journal of Systems, Control and Communications (IJSCC), Vol. 11, No. 3, 2020
Abstract: An area and power efficient FPGA implementation approach of memory built-in self-test (MBIST) is presented in this paper. It is consist of an array of 2-bit linear feedback shift register (LFSR), the switching activity of address generator used in previous MBIST architectures are high. This unwanted switching activity is affecting the power consumption of entire MBIST. We propose the MBIST with ring-based LFSR used to avoid the main problem of power consumption. The 2-bit 2N pattern generator combines with a conventional (N − 2) bit 2(N−2) LFSR and a 2-bit four pattern generator are both controlled separately by a two separate clocks of two different frequencies to generate all possible memory address location of a memory under test. The proposed architecture is implemented on vertex4 FPGA technology in Xilinx software. We showed that results improve the performance of the proposed design by comparing with the existing design.
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