Optimised fault tolerant core-based ASIC design for SRAM
by T. Suresh; Z. Brijet
International Journal of Manufacturing Technology and Management (IJMTM), Vol. 35, No. 6, 2021

Abstract: SRAMs are suitable to the applications of space and other radiation environment. Unfortunately, SRAMs are vulnerable to single event upsets (SEUs) induced by radiation environment's particles. So, the designer needs to validate an efficiency of the developed designs to detect and correct the errors. In this paper, an error-detection Hamming code which can be used to detect single and multiple bit errors and correct these errors in SRAMs has been proposed. It is a novel self-repairing approach for fast fault recovery with an optimised design which requires less number of resources, which can be easily applied to real time complex digital applications. The fault tolerant core is verified using Hamming code and synthesised using Xilinx ISE 14.5 and Cadence RTL compiler targeted to UMC90nm CMOS technology. After the successful synthesis the physical design using the Cadence Encounter has been created. The physical design involves the floor planning, routing and generating a GDS II file. The total optimised area is about 3512mm² with the total power dissipation of about 316.159 μW.

Online publication date: Mon, 21-Mar-2022

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