FPGA-based DFT system design, optimisation and implementation using high-level synthesis Online publication date: Tue, 11-Oct-2022
by Shensheng Tang; Monali Sinare; Yi Xie
International Journal of Computer Applications in Technology (IJCAT), Vol. 69, No. 1, 2022
Abstract: In this paper, a discrete Fourier transform (DFT) algorithm is designed and optimised for the FPGA implementation using the Xilinx VIVADO High-Level Synthesis (HLS) tool. The DFT algorithm is written by C++ programming and simulated for functional verification in the HLS and MATLAB. For hardware validation, the DFT module is packaged as an IP core and tested in a VIVADO project. A Xilinx SDK application written by C language is developed and used for testing the DFT module on a Zynq FPGA development board, ZedBoard. For visualisation of the DFT magnitude spectrum generated in FPGA, a GUI is developed by C# programming and related commands/data can be communicated between the GUI and ZedBoard over the serial port. Experimental results are presented with discussion. The DFT module design, optimisation and implementation as well as the VIVADO project development methods can be extended to other FPGA applications.
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