Efficient hardware architectures of Lilliput lightweight algorithm for image encryption Online publication date: Mon, 07-Nov-2022
by Pulkit Singh; K. Abhimanyu Kumar Patro; Bibhudendra Acharya; Rahul Kumar Chaurasiya
International Journal of Ad Hoc and Ubiquitous Computing (IJAHUC), Vol. 41, No. 4, 2022
Abstract: With the advancement of communication networks, information security has become extremely crucial in storage and transmission. As images are used in most of the networks, hence image security is becoming a challenging task. This paper proposes two hardware architectures of Lilliput lightweight block cipher. These hardware architectures are implemented on FPGA and ASIC platforms compared with state-of-the-art designs. In these architectures, first, 8-bit and then 16-bit serial structures are designed to implement. The serialised designs of 8-bit and 16-bit imply low area by consuming less number of slices. Finally, these serialised architectures are utilised for image encryption with the help of a controller. The simulation results and security analysis for hardware generated encrypted images show the better performance of proposed architectures and stronger resistance against entropy attack, differential attack, and statistical attacks.
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