Modelling and optimisation of high-speed KLEIN architectures on FPGA and ASIC platforms for IoT applications
by Pulkit Singh; Rahul Kumar Chaurasiya; Bibhudendra Acharya
International Journal of Ad Hoc and Ubiquitous Computing (IJAHUC), Vol. 42, No. 4, 2023

Abstract: Security and privacy are serious issues in the internet of things (IoT) emerging areas. The lightweight cryptographic algorithms are immensely important for secure communication in high-speed IoT applications. The objective of this work is to obtain optimised architectures from scalar and pipelined designs from modified KLEIN cipher implemented on field programmable gate arrays (FPGA) and application specific integrated circuits (ASIC) platforms. This analysis is carried out based on examined hardware metrics such as frequency, area, power, and energy consumption. A one-round scalar implementation shows 73.1% and 93.3% lesser power and 70.7% and 93.1% energy efficient compared to one-round pipelined implementation on both platforms. In addition, this paper demonstrates that modelled and optimised implementations of modified KLEIN cipher show good accuracy compared to state-of-the-art design models. Hence, this paper gives general guidelines for all lightweight block ciphers by noticing the behaviour of modified KLEIN cipher.

Online publication date: Fri, 21-Apr-2023

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