Reconfigurable lower-part approximate adder with error-tolerant application: an approach using QCA computing Online publication date: Wed, 29-May-2024
by Angshuman Khan; M.C. Parameshwara; Naeem Maroof
International Journal of Ad Hoc and Ubiquitous Computing (IJAHUC), Vol. 46, No. 2, 2024
Abstract: This work describes a new multi-bit approximate full adder (reconfigurable lower-part) or MAFA(RL) architecture made up of an MSB adder (exact) and an LSB adder (approximate). The MSB adder consists of a handful of 1-bit exact adders. The LSB adder is designed using majority gates with distinct configurations - OR, AND, buffer, constant-0, and constant-1 to justify the reconfigurability of the block. The QCADesigner tool is used to design and test the suggested layout. The recommended design has 4% and 13.3% fewer cell and clock phase counts than the others. The primary advantage of the proposed design is the reconfigurability of a few of its inputs. The image processing application serves as a demonstration of the fault-tolerant functionality of the design. Furthermore, an analysis of image quality metrics (IQM) and other parameters reveals an 11% and 12% improvement in the recommended block's area-delay product (ADP) and normalised ADP (NADP), respectively.
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