FPGA design and implementation of an efficient FIR adaptive filter by adopting CSD based approximate distributed arithmetic architecture Online publication date: Thu, 01-Aug-2024
by C.S. Vinitha
International Journal of Mobile Communications (IJMC), Vol. 24, No. 2, 2024
Abstract: An effective approximate distributed arithmetic (DA) architecture is proposed for adaptive finite impulse response (FIR) filters. The approximate DA architecture is combined with canonical signed digit (CSD) number representation, which is used for reducing the partial products. Additionally, the partial products are added using the Wallace tree adder, which further helps to increase the speed and reduce the filter complexity. The proposed design is encoded in VHDL that are simulated, synthesized and implemented in MATLAB and Xilinx field-programmable gate arrays (FPGA) unit to evaluate the hardware complexity of the filter. The proposed adaptive filter's hardware efficiency in terms of number of slices utilized is 40% less than booth algorithm, and 62% less than basic DA-based adaptive filter. Also, the total power consumption is 20%, 28% and 30% less than booth algorithm, NLMS and DA based filter respectively. This filter operates at higher frequency compared to its previous filter designs.
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