Welded silicon for power electronic devices Online publication date: Tue, 02-Nov-2010
by Colin Parkes, S.J. Neil Mitchell, B. Mervyn Armstrong, Harold S. Gamble, Edmond T.G. Ling
International Journal of Materials and Product Technology (IJMPT), Vol. 11, No. 1/2, 1996
Abstract: The improvement of many silicon power devices can be achieved by the incorporation of high resistivity layers and heavily doped buried regions into the device structure. Until recently epitaxial growth using chemical vapour deposition was the only viable method of achieving lightly doped silicon on a more heavily doped substrate. An alternative approach is the bonding of two silicon wafers. Bonding is achieved by bringing two polished silicon wafers together in a dust-free environment. The present technique employs a wash bath allowing the wafers to be bonded under liquid ensuring minimum contamination. After high temperature annealing the bonded structures can endure all standard processing treatments. Welded PN diodes yielded near-ideal characteristics and NPN bipolar transistors, with the weld interface in the P-base region, were produced with an average minority lifetime for carriers of 5ms. The viability of the process was further demonstrated by the production of large area Gate Turn-off thyristors.
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Materials and Product Technology (IJMPT):
Login with your Inderscience username and password:
Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.
If you still need assistance, please email subs@inderscience.com
Our Blog 
Follow us on Twitter 
Visit us on Facebook