Implementation of a novel LVQ neural network architecture on FPGA
by Najoua Chalbi, Khaled Ben Khalifa, Mohamed Boubaker, Mohamed Hedi Bedoui
International Journal of Artificial Intelligence and Soft Computing (IJAISC), Vol. 2, No. 3, 2010

Abstract: The current study presents the hard implementation methodology of a Learning Vector Quantization (LVQ) neural network on a Field Programmable Gate Array (FPGA) circuit specially suited for fast output applications. The implementation methodology is based on a mixed parallel sequential approach with the use of the L2 norm (Euclidian distance) to measure the distance between the reference vector and the prototype vector. The adopted architecture has been implemented on a device XCV1000 (FPGA Xilinx) and the given results have shown good performances in time, surface and consumption.

Online publication date: Thu, 17-Feb-2011

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

 
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Artificial Intelligence and Soft Computing (IJAISC):
Login with your Inderscience username and password:

Username:        Password:          Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com