FPGA-based parallel architecture for PID control algorithm and HDL co-simulation Online publication date: Sat, 19-Jul-2014
by T. Ananthan; M.V. Vaidyan
International Journal of Embedded Systems (IJES), Vol. 5, No. 4, 2013
Abstract: This paper aims to describe a dedicated high throughput parallel architecture for digital proportional-integral-derivative (PID) controller along with its field programmable gate array (FPGA) and application specific integrated circuit (ASIC) implementations. The processing speed of the controller depends on design of arithmetic units. In this context, this design incorporates parallel multipliers and a parallel adder to enhance the processing speed. This design is deeply pipelined to achieve high throughput. The algorithm is prototyped on Xilinx FPGA and implemented in 180 nm technology using cadence RTL complier. The performance of the controller is analysed by the results from a dc-dc buck converter control system through hardware descriptive language (HDL) co-simulation. Electronic design automation (EDA) simulator link interacts with hardware and software in MATLAB/Simulink environment and in this environment the response of the buck converter control system prior to hardware implementation is shown.
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