Trends toward on-chip networked microsystems Online publication date: Wed, 28-Sep-2005
by Timothy Mark Pinkston, Jeonghee Shin
International Journal of High Performance Computing and Networking (IJHPCN), Vol. 3, No. 1, 2005
Abstract: This survey paper identifies some trends in the application, implementation technology, and processor architecture areas. A taxonomy which captures the influence of these trends on processor microsystems is presented, and the communication needs of various classes of these architectures is also briefly surveyed. We observe a trend toward on-chip networked microsystems derived from logically and physically partitioning the processor architecture. Partitioning the architecture logically enables the parallelism offered by growing application workloads to be well exploited. Partitioning the architecture physically enables the scaling properties of the underlying implementation technology to continue providing increased performance and not be encumbered by chip-crossing wire delay, which no longer is negligible. The impact on future research directions of this paradigm shift in the way microsystems are designed and intraconnected is briefly highlighted.
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