Title: Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers

Authors: Anu Mehra; Vinay Verma; Rana Majumdar; Nidhi Gaur; Alok Kumar; Ansh Awasthi; Chanda Pandey

Addresses: Department of Electronics and Communications, Amity University, Uttar Pradesh, India ' Department of Electronics and Communications, Amity University, Uttar Pradesh, India ' Department of Information Technology, Amity University, Uttar Pradesh, India ' Department of Electronics and Communications, Amity University, Uttar Pradesh, India ' Department of Electronics and Communications, Amity University, Uttar Pradesh, India ' Department of Electronics and Communications, Amity University, Uttar Pradesh, India ' Department of Electronics and Communications, Amity University, Uttar Pradesh, India

Abstract: Multipliers are the basic building blocks of various processors; arithmetic and logical unit and they are widely used in digital signal processing and image processing applications such as convolution, DWT, DCT. In this paper, four separate algorithms for designing binary multipliers are adopted from the ancient Indian Book of Wisdom Sthapatya-veda (an Upa-veda of Atharvaveda). The current work mainly focuses on comparing the power, delay, look up table (LUT), noise margin of different multiplier algorithms using various sutra's of Vedic mathematics which has been implemented on Virtex 7 Board 1.1, using Xilinx Vivado version 14.2.

Keywords: delay; look up table; LUT; power; Vedic multiplier.

DOI: 10.1504/IJISE.2019.102466

International Journal of Industrial and Systems Engineering, 2019 Vol.33 No.2, pp.129 - 140

Received: 06 Aug 2016
Accepted: 16 Dec 2017
Published online: 27 Sep 2019 *

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