Title: Asymmetric gated Ge-Si_0.7Ge_0.3 nHTFET and pHTFET for steep subthreshold characteristics

Authors: Suman Lata Tripathi; Sobhit Saxena

Addresses: School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, Punjab, 144411, India ' School of Electronics and Electrical Engineering, Lovely Professional University, Phagwara, Punjab, 144411, India

Abstract: The miniaturisation of transistors imposes thermal limits on MOSFET structures due to increase in leakage current and static power consumption per unit area of chip below 20 nm technology node. Tunnel FET has potential to reduce static power consumption to design below 20 nm technology within thermal limits thus increases the scope of future scaling trends. A new asymmetric Ge-Si_0.7Ge_0.3 hetero-junction tunnel FET (HTFET) is proposed with different oxide thickness from source and drain side. The asymmetric Ge-Si_0.7Ge_0.3 HTFET has steep subthreshold characteristic, low DIBL with high I_ON/I_OFF current ratio for operating voltage less than 1V. The proposed design can be fabricated easily due to the similar lattice structure of Ge and Si. The I_ON/I_OFF current ratio greater than 10⁸ is achieved for gate length of 15 nm in nHTFET having Pt/HfO₂ as gate contact and oxide material. The lowering of parasitic BJT effect in OFF state condition is also achieved in the same.

Keywords: band to band tunnelling; BTBT; drain induced barrier lowering; DIBL; subthershold slope; SS; hetero-junction; narrow band gap material.

DOI: 10.1504/IJMMP.2019.103172

International Journal of Microstructure and Materials Properties, 2019 Vol.14 No.6, pp.497 - 510

Received: 01 Feb 2019
Accepted: 22 May 2019
Published online: 21 Oct 2019 *

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