Article: Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms Journal: International Journal of Bio-Inspired Computation (IJBIC) 2020 Vol.15 No.1 pp.43 - 51 Abstract: This paper discusses the performance analysis of memetic and genetic algorithms (GA and MA) as the optimising strategy for the design of embedded evolvable hardware. The optimisation algorithm with the fitness evaluation searches for the best configuration to evolve the hardware model. Here, an experimental setup is carried to intrinsically evolve combinational circuits to test the performance of MA and GA. The complete evaluation and evolution is built on a single Virtex 6 (XC6VLX240T-1FFG1156) ML605 Evaluation Kit FPGA. A virtual reconfigurable architecture (VRA) with the hardware fitness circuit is modelled as a second reconfigurable layer over the field programmable gate array (FPGA) to configure the target combinational logic. A FPGA soft core processor evaluates the search algorithm and the best solutions are utilised for the hardware evolution. The experimentation results showed that convergence and evolution time of MA was faster compared to GA when the search space was large. Thus, proving MA is a better option for large search space evaluations for evolvable hardware architectures. Inderscience Publishers - linking academia, business and industry through research

Title: Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms

Authors: Ranjith Chandrasekharan; S.P. Joy Vasantha Rani

Addresses: Faculty of Electronics and Communication Engineering Department, KMCT College of Engineering, Kallanthode, Calicut, Kerala, India ' Faculty of Electronics Engineering Department, MIT Campus, Anna University, Chromepet, Chennai, Tamil Nadu, India

Abstract: This paper discusses the performance analysis of memetic and genetic algorithms (GA and MA) as the optimising strategy for the design of embedded evolvable hardware. The optimisation algorithm with the fitness evaluation searches for the best configuration to evolve the hardware model. Here, an experimental setup is carried to intrinsically evolve combinational circuits to test the performance of MA and GA. The complete evaluation and evolution is built on a single Virtex 6 (XC6VLX240T-1FFG1156) ML605 Evaluation Kit FPGA. A virtual reconfigurable architecture (VRA) with the hardware fitness circuit is modelled as a second reconfigurable layer over the field programmable gate array (FPGA) to configure the target combinational logic. A FPGA soft core processor evaluates the search algorithm and the best solutions are utilised for the hardware evolution. The experimentation results showed that convergence and evolution time of MA was faster compared to GA when the search space was large. Thus, proving MA is a better option for large search space evaluations for evolvable hardware architectures.

Keywords: evolvable hardware; EHW; embedded evolvable hardware; evolutionary algorithm; genetic algorithm; memetic algorithm; MicroBlaze processor; virtual reconfigurable architecture; VRA; evolution speed; evaluation time; combinational circuits; intrinsic evolution; bio-inspired algorithm.

DOI: 10.1504/IJBIC.2020.105850

International Journal of Bio-Inspired Computation, 2020 Vol.15 No.1, pp.43 - 51

Received: 13 Aug 2018
Accepted: 08 Dec 2018
Published online: 16 Mar 2020 *

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Title: Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms

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