Article: A novel technique for minimisation of March test using read equivalent stress Journal: International Journal of Nanomanufacturing (IJNM) 2020 Vol.16 No.2 pp.184 - 201 Abstract: Static random access memory is popularly used in the cache memories due to its infinite and very fast read/write operations. As technology advances, size of devices shrinks and the percent of manufacturing defects in integrated circuits increases significantly which results in different types of faults. The most crucial part regarding testing is achieving maximum fault coverage with minimal test time. March SR+ is one of the test used frequently in the industry, which has a higher percentage of fault detection with a test length of 18N. In this paper, we propose a novel technique to minimise the test time of March SR+. On this basis, we introduce a more efficient alternative to March SR+. The reformulation of March SR+ is essentially based on introducing a particular addressing sequence and read/write data sequence. This modification does not alter the capability of March SR+ to detect the former target faults, but extends the ability of many conventional March-based test solutions in detecting dynamic read destructive faults without any test modification. Moreover, fault detection using the proposed methodology results in a significant reduction of 11.1% in test time and 11.04% in average power consumption. Inderscience Publishers - linking academia, business and industry through research

Title: A novel technique for minimisation of March test using read equivalent stress

Authors: Princy Prince; N.M. Sivamangai

Addresses: Karunya Institute of Technology and Sciences, Karunya Nagar, Coimbatore, Tamil Nadu – 641114, India ' Karunya Institute of Technology and Sciences, Karunya Nagar, Coimbatore, Tamil Nadu – 641114, India

Abstract: Static random access memory is popularly used in the cache memories due to its infinite and very fast read/write operations. As technology advances, size of devices shrinks and the percent of manufacturing defects in integrated circuits increases significantly which results in different types of faults. The most crucial part regarding testing is achieving maximum fault coverage with minimal test time. March SR⁺ is one of the test used frequently in the industry, which has a higher percentage of fault detection with a test length of 18N. In this paper, we propose a novel technique to minimise the test time of March SR⁺. On this basis, we introduce a more efficient alternative to March SR⁺. The reformulation of March SR⁺ is essentially based on introducing a particular addressing sequence and read/write data sequence. This modification does not alter the capability of March SR⁺ to detect the former target faults, but extends the ability of many conventional March-based test solutions in detecting dynamic read destructive faults without any test modification. Moreover, fault detection using the proposed methodology results in a significant reduction of 11.1% in test time and 11.04% in average power consumption.

Keywords: static random access memory; SRAM; word line; March AI; dynamic read destructive fault; DRDF; fault testing; static; conventional; power reduction; March test; read equivalent stress; RES.

DOI: 10.1504/IJNM.2020.106334

International Journal of Nanomanufacturing, 2020 Vol.16 No.2, pp.184 - 201

Received: 16 Oct 2018
Accepted: 16 Aug 2019
Published online: 02 Apr 2020 *

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Title: A novel technique for minimisation of March test using read equivalent stress

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