Title: Intra and inter-core power modelling for single-ISA heterogeneous processors

Authors: Krastin Nikov; Jose Nunez-Yanez

Addresses: Department of Electrical and Electronic Engineering, University of Bristol, Bristol, UK ' Department of Electrical and Electronic Engineering, University of Bristol, Bristol, UK

Abstract: This research presents a systematic methodology for producing accurate power models for single instruction set architecture (ISA) heterogeneous processors. We use the hardware event counters from the processor performance monitoring unit (PMU) to accurately capture the CPU states and ordinary least squares (OLS), assisted by automated event selection algorithms, to compute the power models. Several estimators for single-thread and multi-thread benchmarks are proposed capable of performing power predictions across different frequency levels for one processor as well as between the heterogeneous processors with less than 3% error. The models are compared to related work showing significant improvement in accuracy and good computational efficiency which makes them suitable for run-time deployment.

Keywords: big.LITTLE system-on-chip; linear regression; ordinary least squares; hardware performance events; automated event selection; power modelling; energy efficiency; heterogenous processor; energy prediction.

DOI: 10.1504/IJES.2020.107046

International Journal of Embedded Systems, 2020 Vol.12 No.3, pp.324 - 340

Received: 19 Jun 2018
Accepted: 20 Jan 2019
Published online: 01 May 2020 *

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