Title: Construction of complete minimal test set for single intra-level bridging and stuck-at faults in reversible circuits

Authors: Mousum Handique

Addresses: Department of Computer Science and Engineering, IIT, Guwahati, 781039, Assam, India

Abstract: Reversible logic computing is gaining enough interest in the field of low-power circuit design technology. Moreover, the concept of reversible computing is widely used in quantum circuit computation. Therefore, it has motivated researchers to explore reversible logic as a circuit design alternative. Several problems of synthesis and optimisation of the reversible circuits have been reported in the present literature. In this context, the testing plays an important role in the effective performance of these circuits. For detecting all possible faults in the reversible circuits, numerous fault models have been proposed, where many of the proposed fault models common to conventional logic circuits. In this paper, we consider the problem of testing in the NCT or GT library-based reversible circuits with respect to an efficient test set generation for single intra-level bridging faults and single stuck-at faults. The proposed test generation method has been developed based on the concept of one-to-one mapping mechanism (reversible circuit property). Finally, experimental results show that the generated test is capable of 100% fault coverage for both the fault models and also the results are compared with the existing methods for analysing the test set size.

Keywords: complete test set; fault description list; FDL; reversible circuits; single intra-level bridging faults; single stuck-at faults; SSF.

DOI: 10.1504/IJAIP.2021.113333

International Journal of Advanced Intelligence Paradigms, 2021 Vol.18 No.3, pp.373 - 397

Received: 28 Dec 2017
Accepted: 12 Mar 2018
Published online: 01 Mar 2021 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article