Title: Design and implementation of DVR as fault current limiter in DFIG during grid faults

Authors: Sheena Latif; J.S. Savier

Addresses: Faculty of Engineering, Department of Electrical and Electronics Engineering, College of Engineering, Trivandrum, Kerala, India ' Faculty of Engineering, Department of Electrical and Electronics Engineering, College of Engineering, Trivandrum, Kerala, India

Abstract: The wind grid code requirements for low voltage ride through of various countries demand the DFIG to remain connected to the grid during the event of occurrence of voltage dip. Dynamic voltage restorer supports the grid and enables the uninterrupted operation of DFIGs during partial voltage sag. The increased depth of voltage sag causes rise in stator current and eventual increases in rotor current and dc link capacitance voltage of DFIG. This paper focuses on an enhanced topology of fault current limiting dynamic voltage restorer for supporting the grid and DFIG during fault currents caused by severe voltage dips. The optimal parameters design of fault current limiting dynamic voltage restorer for DFIG systems are discussed in detail. The novelty of the proposed control strategy of fault current limiting dynamic voltage restorer is justified by comparing its performance with the existing methods of fault current mitigations popular with wind farms such as crowbar protection and dc chopper methods. Analytical results of fault current limiting dynamic voltage restorer with DFIG in time domain prove to have the combined effect of both crowbar protection and dc chopper-controlled rotor protection during severe unbalanced grid faults.

Keywords: fault current rise; low voltage ride through; LVRT; dynamic voltage restorer; DVR; FCLDVR; fault current control; doubly fed induction generator; DFIG.

DOI: 10.1504/IJESMS.2021.114976

International Journal of Engineering Systems Modelling and Simulation, 2021 Vol.12 No.1, pp.38 - 53

Received: 21 Jun 2019
Accepted: 23 Mar 2020
Published online: 13 May 2021 *

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