Title: New safe reliable design methodologies examined by fault injection testing and Monte Carlo simulation: tolerating shared-memory interferences in multicore architectures

Authors: Abdullah El-Bayoumi

Addresses: TTTech Auto Iberia, TTTech Group, Barcelona 08029, Spain; Electronics and Electrical Communications Engineering Department, Cairo University, Giza 12613, Egypt

Abstract: Nowadays, the automotive industry utilises multicore processors to meet autonomous driving requirements. This imposes a higher complexity on the development and the verification of software applications. Compliance to the ISO 26262 safety standard increases this complexity. In this paper, means of shared-memory interferences that affect Automotive Safety Integrity Level (ASIL)-D multicore architectures have been addressed. This work proposes new safety mechanisms to detect and react to systematic and random transient memory faults as follows: 1) an enhanced software partitioning design pattern; 2) a new methodology on the memory protection unit; 3) an improved stack monitoring mechanism. New safe and reliable design configurations are introduced. The proposed safety mechanisms have been evaluated for Aurix multicore targets with suggestions to have a fully compliant architecture followed with ISO 26262 methods and principles of tolerating memory interferences. A novel fault injection platform is presented to show the experimental results with a Monte Carlo simulation proof of concept.

Keywords: functional safety; fault detection; software architecture; real-time operating system; fault reaction; multicore processor; memory protection; freedom from interference; fault tolerance; safety mechanism; ISO 26262; reliability; fault injection; Monte Carlo.

DOI: 10.1504/IJES.2021.117956

International Journal of Embedded Systems, 2021 Vol.14 No.4, pp.409 - 420

Received: 19 Jun 2020
Accepted: 15 Nov 2020
Published online: 05 Oct 2021 *

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