Article: Dual-scan architecture for 2D discrete wavelet transform using modified lifting algorithm Journal: International Journal of Systems, Control and Communications (IJSCC) 2021 Vol.12 No.4 pp.327 - 339 Abstract: An efficient architecture of discrete wavelet transform (DWT) in two-dimension (2D) is presented in this paper. The proposed structure has a higher hardware efficiency and better performance than the other DWT structures. The conventional lifting scheme is modified to reduce the latency and critical path to one multiplier delay (1Tm). The processing speed of the architecture is increased by introducing four pipeline stages in the DWT structure. Cohen-Daubechies-Feauveau (CDF) 9/7 wavelet filter is implemented in the paper. The data scanning of the input image for processing is done in Z-fashion. The computation time of an N × N image is N2/2 and the temporal buffer requirement is 4N. The DWT architecture developed based on the modified lifting scheme has a regular data flow with a throughput rate of two. Very high speed hardware description language (VHDL) is used to describe the digital design. The architecture is implemented on CADENCE tool with CMOS 180 nm technology. The results after comparison indicate that the proposed architecture is hardware efficient and memory utilisation is reasonable as a result of which this structure can be used in real-time image and video compression. Inderscience Publishers - linking academia, business and industry through research

Title: Dual-scan architecture for 2D discrete wavelet transform using modified lifting algorithm

Authors: Rohan Pinto; Jennifer C. Saldanha

Addresses: Department of Electronics and Communication Engineering, St. Joseph Engineering College, Mangalore, India; Affiliated to: Visvesvaraya Technological University, India ' Department of Electronics and Communication Engineering, St. Joseph Engineering College, Mangalore, India; Affiliated to: Visvesvaraya Technological University, India

Abstract: An efficient architecture of discrete wavelet transform (DWT) in two-dimension (2D) is presented in this paper. The proposed structure has a higher hardware efficiency and better performance than the other DWT structures. The conventional lifting scheme is modified to reduce the latency and critical path to one multiplier delay (1T_m). The processing speed of the architecture is increased by introducing four pipeline stages in the DWT structure. Cohen-Daubechies-Feauveau (CDF) 9/7 wavelet filter is implemented in the paper. The data scanning of the input image for processing is done in Z-fashion. The computation time of an N × N image is N²/2 and the temporal buffer requirement is 4N. The DWT architecture developed based on the modified lifting scheme has a regular data flow with a throughput rate of two. Very high speed hardware description language (VHDL) is used to describe the digital design. The architecture is implemented on CADENCE tool with CMOS 180 nm technology. The results after comparison indicate that the proposed architecture is hardware efficient and memory utilisation is reasonable as a result of which this structure can be used in real-time image and video compression.

Keywords: discrete wavelet transform? DWT? lifting scheme? VLSI architecture? pipeline.

DOI: 10.1504/IJSCC.2021.118587

International Journal of Systems, Control and Communications, 2021 Vol.12 No.4, pp.327 - 339

Received: 09 Aug 2019
Accepted: 20 Oct 2020
Published online: 29 Oct 2021 *

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Title: Dual-scan architecture for 2D discrete wavelet transform using modified lifting algorithm

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