Title: FPGA implementation of polar codes for 5G eMBB control channels

Authors: G. Aparna; Raparla Swathi; M. Kezia Joseph; C.N. Sujatha; B. Rajendra Naik

Addresses: University College of Engineering, Osmania University, Hyderabad, Telangana, India ' V. Potluri Siddhartha Institute of Technology, Vijayawada, Andhra Pradesh, India ' Stanley College of Engineering and Technology for Women, Nampally, Hyderabad, India ' Sreenidhi Institute of Science and Technology (SNIST), Hyderabad, Telangana, India ' University College of Engineering, Osmania University, Shivam Road, Hyderabad, Telangana, India

Abstract: The rapid growth in wireless communications and information technology over a decade is demanding advanced wireless technologies development. Design and implementation of channel codes for different code lengths (N) and varying code rates (R) to handle the latency and the hardware requirements for enhanced mobile broad band (eMBB) control channel standards like 5G is a challenging issue at present. Polar codes are treated as a solution to the above defined design aspects to fulfil the requirements by the 3rd Generation Partnership Project (3GPP). Therefore, a VLSI architecture for polar codes implementation using SCLD method based on LLR approach is designed and simulated using VHDL programming, ISE Navigator 14.2, HDL synthesiser on the target FPGA device XC6vlx760-1-ffl760 for analysing various code lengths N [128, 256, 512] as inputs and code rates R [1/6, 1/3, 1/2] in this paper.

Keywords: enhanced mobile broad band; eMBB; 5G-fifth generation; successive cancellation list; SCL; successive cancellation list decoder; log-likelihood ratio log; LLR; control channels; FPGA.

DOI: 10.1504/IJUWBCS.2021.119139

International Journal of Ultra Wideband Communications and Systems, 2021 Vol.4 No.3/4, pp.170 - 181

Received: 08 Oct 2020
Accepted: 15 Jan 2021
Published online: 24 Nov 2021 *

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