Title: Automatic generation of VHDL code for a railway interlocking system

Authors: Martín N. Menéndez; Santiago Germino; Facundo S. Larosa; Ariel Lutenberg

Addresses: Laboratorio de Sistemas Embebidos, CONICET-GICSAFe, Facultad de Ingeniería, Universidad de Buenos Aires, Paseo Colón 850, Buenos Aires, Argentina ' Laboratorio de Sistemas Embebidos, CONICET-GICSAFe, Facultad de Ingeniería, Universidad de Buenos Aires, Paseo Colón 850, Buenos Aires, Argentina ' Grupo de aplicaciones en sistemas embebidos, CONICET-GICSAFe, Facultad Regional Haedo, Universidad Tecnológica Nacional, Buenos Aires, Argentina ' Laboratorio de Sistemas Embebidos, CONICET-GICSAFe, Facultad de Ingeniería, Universidad de Buenos Aires, Paseo Colón 850, Buenos Aires, Argentina

Abstract: This article introduces a novel technique to automatically analyse a railway network geographical representation and produce a suitable FPGA railway interlocking system by generating its VHDL hardware description. This approach accelerates the design, implementation and testing phases on different topologies. We review the automated tools developed - which are part of a comprehensive workflow - and present the results for topologies of varying complexities.

Keywords: railway interlocking system; automatic code generation; ACG; graph networks; FPGA; VHDL.

DOI: 10.1504/IJES.2021.121088

International Journal of Embedded Systems, 2021 Vol.14 No.6, pp.544 - 552

Received: 25 Nov 2020
Accepted: 02 May 2021
Published online: 24 Feb 2022 *

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