Article: Comparative analysis between different approaches for single-phase PLLs Journal: International Journal of Power Electronics (IJPELEC) 2022 Vol.16 No.1 pp.34 - 60 Abstract: This paper presents a comparative analysis between two distinct synchronising circuits, which are usually applied as the core of control algorithms for single-phase power quality applications. One of these synchronising circuits corresponds to a single-phase phase-locked loop (PLL), implemented in α-β coordinates (αβ-PLL), whereas the other one corresponds to the enhanced PLL (E-PLL). The major contribution of this paper is to present a single-phase PLL oriented to power quality applications, with a very simple structure, capable to be synchronised with the fundamental component of an input signal (voltage or current), even considering substantial disturbances, such as, frequency deviations, phase shifts, harmonic components and amplitude variations. Simulation and experimental results, involving these two synchronising circuits submitted to three different test cases, are provided in order to compare their transient and steady-state performance. Moreover, a comparison involving the processing speed and memory requirements of these synchronising circuits in the DSP TMS320F28335 is also presented. Inderscience Publishers - linking academia, business and industry through research

Title: Comparative analysis between different approaches for single-phase PLLs

Authors: Luís Fernando Corrêa Monteiro; J.G. Pinto; Vitor Monteiro; Carlos Couto; João Afonso

Addresses: Department of Electronics and Communications, Rio de Janeiro State University, Rio de Janeiro, Brazil ' Centro ALGORITMI, University of Minho, Guimaraes, Portugal ' Centro ALGORITMI, University of Minho, Guimaraes, Portugal ' Centro ALGORITMI, University of Minho, Guimaraes, Portugal ' Centro ALGORITMI, University of Minho, Guimaraes, Portugal

Abstract: This paper presents a comparative analysis between two distinct synchronising circuits, which are usually applied as the core of control algorithms for single-phase power quality applications. One of these synchronising circuits corresponds to a single-phase phase-locked loop (PLL), implemented in α-β coordinates (αβ-PLL), whereas the other one corresponds to the enhanced PLL (E-PLL). The major contribution of this paper is to present a single-phase PLL oriented to power quality applications, with a very simple structure, capable to be synchronised with the fundamental component of an input signal (voltage or current), even considering substantial disturbances, such as, frequency deviations, phase shifts, harmonic components and amplitude variations. Simulation and experimental results, involving these two synchronising circuits submitted to three different test cases, are provided in order to compare their transient and steady-state performance. Moreover, a comparison involving the processing speed and memory requirements of these synchronising circuits in the DSP TMS320F28335 is also presented.

Keywords: phase-locked loop; PLL; αβ-PLL; enhanced PLL; E-PLL; digital signal processor; DSP; power quality.

DOI: 10.1504/IJPELEC.2022.124267

International Journal of Power Electronics, 2022 Vol.16 No.1, pp.34 - 60

Received: 17 Jul 2019
Accepted: 11 Jun 2020
Published online: 21 Jul 2022 *

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Title: Comparative analysis between different approaches for single-phase PLLs

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