Title: Knowledgeable network-on-chip accelerator for fast and accurate simulations using supervised learning algorithms and multiprocessing

Authors: Anil Kumar; Basavaraj Talawar

Addresses: Department of Computer Science and Engineering, National Institute of Technology Karnataka Surathkal, Mangalore, 575 025, Karnataka, India ' Department of Computer Science and Engineering, National Institute of Technology Karnataka Surathkal, Mangalore, 575 025, Karnataka, India

Abstract: In a multi-processor system-on-chip (MPSoC) environment, networks-on- chip (NoC) is becoming the de-facto scaling communication technique. One of the most significant techniques used in NoC for analysing and testing new architectures is simulations. Simulation is one of the main tools used in NoC for analysing and testing new architectures. To achieve the best performance vs. cost tradeoff, simulators have become an essential tool. Software simulators are too slow for evaluating large-scale NoCs. To overcome this problem we propose an NoC Accelerator named knowledgeable network-on-chip accelerator (KNoC) which can be used to analyse various NoC architectures. The proposed accelerator is built using machine learning (ML) algorithms and multiprocessing to predict the design parameters of NoCs with a fixed and accurate delay between nodes of large-scale architectures. The KNoC results were compared to the widely used cycle-accurate Booksim simulator. KNoC showed an error rate of less than 6% and an overall speedup of up to 12 Kx.

Keywords: NoC; network-on-chip; Floorplan; performance modelling; simulation; machine learning; prediction; regression; decision tree; Booksim; performance evaluation; power; area; router; traffic pattern.

DOI: 10.1504/IJIEI.2022.125867

International Journal of Intelligent Engineering Informatics, 2022 Vol.10 No.2, pp.160 - 182

Received: 06 Sep 2020
Accepted: 30 Nov 2021
Published online: 30 Sep 2022 *

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