Title: FPGA-based DFT system design, optimisation and implementation using high-level synthesis

Authors: Shensheng Tang; Monali Sinare; Yi Xie

Addresses: Department of Electrical and Computer Engineering, St. Cloud State University, St. Cloud, Minnesota, USA ' Department of Electrical and Computer Engineering, St. Cloud State University, St. Cloud, Minnesota, USA ' School of Computer Science and Engineering, Sun Yat-Sen University, Guangzhou, China

Abstract: In this paper, a discrete Fourier transform (DFT) algorithm is designed and optimised for the FPGA implementation using the Xilinx VIVADO High-Level Synthesis (HLS) tool. The DFT algorithm is written by C++ programming and simulated for functional verification in the HLS and MATLAB. For hardware validation, the DFT module is packaged as an IP core and tested in a VIVADO project. A Xilinx SDK application written by C language is developed and used for testing the DFT module on a Zynq FPGA development board, ZedBoard. For visualisation of the DFT magnitude spectrum generated in FPGA, a GUI is developed by C# programming and related commands/data can be communicated between the GUI and ZedBoard over the serial port. Experimental results are presented with discussion. The DFT module design, optimisation and implementation as well as the VIVADO project development methods can be extended to other FPGA applications.

Keywords: FPGA; DFT; IP core; VIVADO HLS; C/C++; Verilog; C#; optimisation; hardware validation.

DOI: 10.1504/IJCAT.2022.126091

International Journal of Computer Applications in Technology, 2022 Vol.69 No.1, pp.47 - 61

Received: 10 Jun 2021
Accepted: 17 Jul 2021
Published online: 11 Oct 2022 *

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