Article: Analysing the potential of transport triggered architecture for lattice-based cryptography algorithms Journal: International Journal of Embedded Systems (IJES) 2022 Vol.15 No.5 pp.404 - 420 Abstract: Lattice-based structures offer numerous possibilities for post-quantum cryptography. Recently, many post-quantum cryptography algorithms have been built on hard lattice problems. The three of the remaining four algorithms in the final round of the NIST Standardization Process rely on lattice-based methods. However, suitable processor architectures for these algorithms have not been sufficiently investigated. This study examines the potential advantages of transport triggered architecture for these algorithms. We compare popular 64-bit RISC-V processors with our conceptual transport triggered architecture processor over reference software implementations. Our processor provides better results than RISC-V competitors, regardless of the algorithm. It seems to be up to 3× faster, 1.6×-2× smaller, and consumes 1.3×-3.6× less energy than the compared RISC-V cores. Thus, an alternative base architecture is proposed for post-quantum cryptography processor development for embedded systems. The most critical shortcoming of the proposed architecture is the lack of compatible intellectual property core support for system-on-chip designs. We share comparative analyses with test results for different core configurations. Inderscience Publishers - linking academia, business and industry through research

Title: Analysing the potential of transport triggered architecture for lattice-based cryptography algorithms

Authors: Latif Akçay; Berna Örs Yalçın

Addresses: Department of Electrical and Electronics Engineering, Bayburt University, Bayburt, 69000, Turkey Fax: +90-(458)-211-11-77 ' Electronics and Communication Engineering Faculty, Istanbul Technical University, Istanbul, 34467, Turkey Fax: +90-(212)-285-29-10

Abstract: Lattice-based structures offer numerous possibilities for post-quantum cryptography. Recently, many post-quantum cryptography algorithms have been built on hard lattice problems. The three of the remaining four algorithms in the final round of the NIST Standardization Process rely on lattice-based methods. However, suitable processor architectures for these algorithms have not been sufficiently investigated. This study examines the potential advantages of transport triggered architecture for these algorithms. We compare popular 64-bit RISC-V processors with our conceptual transport triggered architecture processor over reference software implementations. Our processor provides better results than RISC-V competitors, regardless of the algorithm. It seems to be up to 3× faster, 1.6×-2× smaller, and consumes 1.3×-3.6× less energy than the compared RISC-V cores. Thus, an alternative base architecture is proposed for post-quantum cryptography processor development for embedded systems. The most critical shortcoming of the proposed architecture is the lack of compatible intellectual property core support for system-on-chip designs. We share comparative analyses with test results for different core configurations.

Keywords: transport triggered architecture; TTA; RISC-V; lattice-based cryptography; post-quantum cryptography; PQC; embedded systems; application-specific processor.

DOI: 10.1504/IJES.2022.127164

International Journal of Embedded Systems, 2022 Vol.15 No.5, pp.404 - 420

Received: 15 Feb 2022
Received in revised form: 10 Jun 2022
Accepted: 02 Jul 2022
Published online: 23 Nov 2022 *

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Title: Analysing the potential of transport triggered architecture for lattice-based cryptography algorithms

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