Title: A low power transistor level FIR filter implementation using CMOS 45 nm technology

Authors: M. Balaji; N. Padmaja

Addresses: Research Scholar, Department of ECE, Jawaharlal Nehru Technological University Ananthapur, Ananthapuramu, 515002, India ' Department of ECE, Sree Vidyanikethan Engineering College, Tirupati, 517101, Andhra Pradesh, India

Abstract: Digital finite impulse response (FIR) filters are widely used in signal processing fields, due to their stability and linear-phase property. In this paper, the low area FIR filter is designed by proposing the optimal array multiplier (OAM) and optimal full adder (OFA) to minimise the resources. The number of adders used in the OAM is decreased by replacing all the half and full adders of conventional multiplier with the OFA. The buffer circuit is designed in the OFA for avoiding the noise, glitches and threshold issue. The proposed OAM-OFA-FIR architecture is designed using Cadence virtuoso software with 45 nm technology and it is analysed in terms of area, power and delay. The existing methods used to evaluate the OAM-OFA-FIR architecture are FIR filter design using Radix-2 algorithm and look-up-table carry select adder (LCSLA), and Vedic design (VD) and carry look-ahead adder (CLA). The area of the OAM-OFA-FIR architecture is 1755 um², which is less when compared to the existing methods.

Keywords: area; delay; FIR; finite impulse response filter; OAM; optimal array multiplier; OFA; optimal full adder; power.

DOI: 10.1504/IJNT.2023.131120

International Journal of Nanotechnology, 2023 Vol.20 No.1/2/3/4, pp.390 - 409

Received: 15 Nov 2021
Accepted: 17 Mar 2022
Published online: 31 May 2023 *