Title: Design of high speed and low power multiplier using dual-mode square adder

Authors: B. Jaya Lakshmi; R. Ramana Reddy; Naresh K. Darimireddy

Addresses: Department of ECE, Lendi Institute of Engineering and Technology, Vizianagaram, Andhra Pradesh, India ' Department of ECE, JNTUA College of Engineering, Pulivendula, Kadapa, Andhrapradesh, India ' Department of ECE, Lendi Institute of Engineering and Technology, Vizianagaram, Andhra Pradesh, India

Abstract: Adders are the basic building blocks in analogue and digital circuits for implementing arithmetic operations. Different adder designs are reported to obtain high speed, less area and low power dissipation. Dual mode logic (DML) and dual mode addition (DMADD) techniques can be used to achieve low power and high speed addition. Adders are the main blocks in multipliers. In this paper Braun multiplier is implemented using dual-mode (DM) square adder. The DM square adder architecture is a combination of DML and DMADD techniques. By incorporating the DM square adder in processors, power dissipation can be reduced. The full adder used in dual-mode square adder is static energy recovery full (SERF) adder which is faster and consumes less power compared to conventional full adder. For Braun multiplier using DM square adder power consumption is reduced by 63.54% and speed is increased by 90%. The proposed designs are implemented using mentor graphics tools in 130 nm technology.

Keywords: dual mode logic; DML; dual mode addition; DMADD; DM square adder; SERF adder; Braun multiplier; low power.

DOI: 10.1504/IJSISE.2023.133653

International Journal of Signal and Imaging Systems Engineering, 2023 Vol.12 No.4, pp.167 - 177

Received: 30 Sep 2018
Accepted: 08 Mar 2019
Published online: 28 Sep 2023 *