Title: Real life implementation of an energy-efficient adaptive advance encryption design on FPGA

Authors: Neeraj Bisht; Bishwajeet Pandey; Sandeep Kumar Budhani

Addresses: Graphic Era Hill University, Bhimtal Campus, India' Jain University, Bengaluru, India ' Graphic Era Hill University, Bhimtal, India

Abstract: Advanced encryption standards (AES) is a mainstream algorithm regularly employed by numerous applications for encryption and decryption purposes. A significant disadvantage of the AES algorithm is its high power consumption. In this research, experimental results are used to compare the on-chip energy consumption and junction power needs of AES algorithms. Five unique FPGAs and four distinct frequencies are used in these tests. Based on the findings, it was found that all FPGAs performed optimally at a frequency of 1.6 GHz. Compared to the worst performing FPGA Artix-7, Kintex-7 Low Voltage used 21.34% less on-chip power during encryption and 20.5% less during decryption. This work validates the considerable improvement in power efficiency by comparing the proposed architecture's on-chip energy consumption figures to those of other existing models. It is suggested to use a 1.60 GHz Kintex-7 Low Voltage processor to run the AES encryption and decryption algorithms.

Keywords: green computing; Advanced Encryption Standards; AES; field programmable gate array; FPGA; on-chip energy usage; junction temperature.

DOI: 10.1504/IJES.2023.136378

International Journal of Embedded Systems, 2023 Vol.16 No.2, pp.105 - 116

Received: 22 Nov 2022
Accepted: 16 May 2023
Published online: 31 Jan 2024 *

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