Title: Parallel processing for block ciphers on a fault tolerant networked processor array

Authors: Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Jungsook Yang, Nader Bagherzadeh

Addresses: Department of Electrical Engineering and Computer Science, University of California, Irvine, California, 92697-2625, USA. ' Department of Electrical Engineering and Computer Science, University of California, Irvine, California, 92697-2625, USA. ' Department of Electrical Engineering and Computer Science, University of California, Irvine, California, 92697-2625, USA. ' Department of Electrical Engineering and Computer Science, University of California, Irvine, California, 92697-2625, USA. ' Department of Electrical Engineering and Computer Science, University of California, Irvine, California, 92697-2625, USA

Abstract: The computational performance of network-on-chip (NoC) and multi-processor system-on-chip (MPSoC) for implementing cryptographic block ciphers can be improved by exploiting parallel and pipelined execution. In this paper, we present a parallel and pipeline processing method for block cipher algorithms using purely software implementation on an NoC. Algorithms are decomposed into task loops, functions and data flow for parallel and pipeline execution. Tasks are allocated by the proposed mapping strategy to each processing element (PE). In order to provide fault tolerance on nanoscale NoC circuits, we add Hamming error correction code (ECC) encoder and decoder at the network interface. The proposed parallel block cipher algorithm implementation on the fault tolerant NoC is simulated by using networked processor array (NePA), the cycle-accurate SystemC and hardware description language (HDL) model platform. Our parallel software implementation method on a multicore NoC architecture has the advantage of flexibility compared with traditional ASIC solutions. In addition, the simulation result presents that the parallel and pipeline processing approach for software block ciphers can be implemented on various NoC platforms which have different complexities and constraints.

Keywords: security; block ciphers; networked processors; network-on-chip; nanoscale NoC; parallel processing; pipeline processing; software implementation; error correction code; ECC; fault tolerance; high performance systems architecture; simulation.

DOI: 10.1504/IJHPSA.2010.034537

International Journal of High Performance Systems Architecture, 2010 Vol.2 No.3/4, pp.156 - 167

Received: 02 Sep 2009
Accepted: 05 Jan 2010
Published online: 07 Aug 2010 *

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