Title: Instruction set extensions for the advanced encryption standard on a multithreaded software defined radio platform

Authors: Christipher Jenkins, Michael Schulte, John Glossner

Addresses: Madison Embedded Systems and Architectures Laboratory, Electrical and Computer Engineering Department, University of Wisconsin-Madison, 3632 Engineering Hall, 1415 Engineering Drive, Madison, WI 53706-1691, USA. ' Madison Embedded Systems and Architectures Laboratory, Electrical and Computer Engineering Department, University of Wisconsin-Madison, 3632 Engineering Hall, 1415 Engineering Drive, Madison, WI 53706-1691, USA. ' Sandbridge Technologies, 120 White Plains Road, 4th Floor, Tarrytown, NY 10591, USA

Abstract: Software-defined radio (SDR) is an emerging technology that facilitates having multiple wireless communication protocols on one device. Previous work has shown that current wireless communication protocols can run on this class of device while consuming significant processing power. Next generation wireless networks require speeds in excess of 50 Mbps. Some of the fastest software implementations of the advanced encryption standard (AES) only achieve 20 Mbps on our reference platform. In order to have secure software-defined radio, the security processing gap must be addressed. This paper presents instruction set architecture (ISA) extensions for the sandblaster digital signal processor (DSP). The sandblaster DSP is a multithreaded processor for SDR that issues multiple operations each cycle and supports vector operations. Our proposed ISA extensions and hardware designs provide significant performance improvements for AES cryptography and should also work well with other types of embedded processors.

Keywords: advanced encryption standard; AES cryptography; multithreaded; security; software defined radio; SDR; instruction set extensions; ISA; hardware design; wireless networks; sandblaster DSP; digital signal processing; embedded processors.

DOI: 10.1504/IJHPSA.2010.034541

International Journal of High Performance Systems Architecture, 2010 Vol.2 No.3/4, pp.203 - 214

Received: 01 Oct 2009
Accepted: 10 Mar 2010
Published online: 07 Aug 2010 *

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