Title: Partitioning and scheduling technique for run time reconfigured systems

Authors: Bouraoui Ouni, Ramzi Ayadi, Abdellatif Mtibaa

Addresses: Laboratory of Electronic and Microelectronic (E.μ.M), Faculty of Sciences at Monastir, 5000, Monastir, Tunisia. ' Laboratory of Electronic and Microelectronic (E.μ.M), Faculty of Sciences at Monastir, 5000, Monastir, Tunisia. ' Laboratory of Electronic and Microelectronic (E.μ.M), Faculty of Sciences at Monastir, 5000, Monastir, Tunisia

Abstract: With tremendous improvement in FPGA technologies over the last decade, various high performances, low cost FPGAs are now available. This has enabled the development of cost effective, high speed reconfigurable boards called run time reconfigured (RTR) system. These boards, due to the abundant hardware resource available, enhance the amount of design parallelism by several magnitudes in comparison to ASIC designs of comparable cost. The advent of such high performance FPGA boards has brought a new research problem: the temporal partitioning problem. In the literature, the main objective of related algorithms in this field is to find the minimal execution time of the input graph on a fixed-size of area. However, this paper focuses on introducing a new temporal partitioning algorithm. It divides the input task graph into an optimal number of partitions and puts each task in the appropriate partition in order to decrease the transfer of data required between partitions of the design.

Keywords: temporal partitioning; run time reconfigurable systems; RTR; scheduling; algorithm architecture adequacy; FPGA boards; field programmable gate arrays.

DOI: 10.1504/IJCAET.2011.037869

International Journal of Computer Aided Engineering and Technology, 2011 Vol.3 No.1, pp.77 - 91

Published online: 30 Sep 2014 *

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