Title: Modified VLSI implementation of DA-DWT for image compression

Authors: M. Nagabushanam; P. Cyril Prasanna Raj; S. Ramachandran

Addresses: Department of Electronics and Communication Engineering, M.S. Ramaiah Institute of Technology, MSR Nagar, MSRIT Post, Bangalore 560 054, Karnataka, India ' Department of EEE, M.S. Ramaiah School of Advanced Studies, #470-P, Peenya Industrial Area,4th Phase, Bangalore 560 058, Karnataka, India ' Department of Electronics & Communication Engineering, S.J. Balagangadhara Institute of Technology, Uttarahalli Main Road, Bangalore 560 054, Karnataka, India

Abstract: The wavelet transformation is a widely used technique for image processing application. Hence compared to traditional transforms such as the Fast Fourier Transform (FFT) and Discrete Cosine Transform (DCT), wavelet transform holds both time and frequency information, based on a multi-resolution analysis framework. There is a growing need to embed it into a real system. Field Programmable Gate Array (FPGA) implementation of Discrete Wavelet Transform (DWT) results in higher processing speed and lower costs when compared to other implementation methods. In this work a modified DA which performs low-pass and high-pass filtering improves the computational speed of DWT. A 9/7 filter is designed using modified DA architecture to perform low-pass and high-pass filtering. By using optimised DA architecture the LUT size is reduced from 2⁹ to 2⁴ locations in 9th order filter and 2⁷ to 2⁴ in 7th order filter. The design is verified in a Verilog HDL simulator and implemented on XILINX Virtex5 FPGA board.

Keywords: image compression; DWT; discrete wavelet transform; distributive arithmetic; FPGA; field programmable gate arrays; high speed processing; image processing.

DOI: 10.1504/IJSISE.2012.049853

International Journal of Signal and Imaging Systems Engineering, 2012 Vol.5 No.3, pp.167 - 174

Received: 12 Nov 2010
Accepted: 28 Jun 2011
Published online: 31 Dec 2014 *

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