Title: Design techniques for variability mitigation

Authors: Shady Agwa; Eslam Yahya; Yehea Ismail

Addresses: Center of Nanoelectronics and Devices (CND), American University in Cairo, Zewail City of Science and Technology, Sheikh Zayed District, 6th of October City, 12588, Giza, Egypt ' Center of Nanoelectronics and Devices (CND), American University in Cairo, Zewail City of Science and Technology, Sheikh Zayed District, 6th of October City, 12588, Giza, Egypt; Benha Faculty of Engineering, Benha University, Fareed Nada St., Benha, Qaliobia, Egypt ' Center of Nanoelectronics and Devices (CND), American University in Cairo, Zewail City of Science and Technology, Sheikh Zayed District, 6th of October City, 12588, Giza, Egypt

Abstract: As the fabrication technology migrated towards the nanometre scale, 22 nm and beyond, yield enhancement has become one of the challenges facing the integrated circuits design community. Delay and power consumption of the manufactured chips deviate from their predesigned values due to process, voltage and temperature (PVT) variations. This deviation can lead to a considerable loss in yield and reliability. In this paper, we classify and survey the approaches developed to mitigate the PVT variations on the circuit and architectural levels.

Keywords: yield enhancement; variability mitigation; correlated clock skewing; thermal induced time variability; domino logic; adaptive voltage; frequency scaling; programmable clock; integrated circuits; circuit design; nanotechnology; architecture design; process variations; voltage variations; temperature variations; nanoelectronics; yield loss; reliability.

DOI: 10.1504/IJCAD.2013.057450

International Journal of Circuits and Architecture Design, 2013 Vol.1 No.1, pp.20 - 40

Received: 06 Mar 2013
Accepted: 05 Apr 2013
Published online: 05 Jul 2014 *