Title: Fault-tolerant architecture for serial-parallel multipliers

Authors: Aida O. Abd El-Gawad

Addresses: Computer and Control Dept., Faculty of Engineering, El-Mansoura University, El-Mansoura, Egypt

Abstract: An efficient fault-tolerant architecture for use in serial-parallel multipliers is proposed. This architecture uses a time redundancy method together with the technique of a fast serial-parallel multiplier to achieve both error detection and error location with small time and hardware overheads. The design is most suitable for use in VLSI circuits and digital signal processing applications where serial data is available.

Keywords: fault tolerant architecture; serial-parallel multipliers; time redundancy; fault tolerance; error detection; error location; VLSI circuits; digital signal processing; DSP.

DOI: 10.1504/IJCAT.1998.062190

International Journal of Computer Applications in Technology, 1998 Vol.11 No.1/2, pp.118 - 126

Published online: 01 Jun 2014 *

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