Title: Combining ALU chaining with two-direction address renaming load value prediction

Authors: Lin Meng; Tomonori Izumi; Kei Ichino; Nobuhiro Moriwaki; Shigeru Oyanagi

Addresses: Department of Electronic and Computer Engineering, Ritsumeikan University, Noji-Higashi 1-1-1, Kusatsu, Shiga, 525-8577, Japan ' Department of Electronic and Computer Engineering, Ritsumeikan University, Noji-Higashi 1-1-1, Kusatsu, Shiga, 525-8577, Japan ' College of Information Science and Engineering, Ritsumeikan University, Noji-Higashi 1-1-1, Kusatsu, Shiga, 525-8577, Japan ' College of Information Science and Engineering, Ritsumeikan University, Noji-Higashi 1-1-1, Kusatsu, Shiga, 525-8577, Japan ' College of Information Science and Engineering, Ritsumeikan University, Noji-Higashi 1-1-1, Kusatsu, Shiga, 525-8577, Japan

Abstract: Instruction level parallelism is one of the basic ways of increasing the performance of current processors. ALU chaining (chain technique) and load value prediction have been proposed for improving instruction level parallelism. Specifically, ALU chaining aims to reduce data dependence. However, it cannot do this when the instruction being depended upon is load instruction. Load value prediction is an effective method for reducing load delay, but the current predictor cannot deliver a good performance because that some predictors just predict few load instructions or some predictors' prediction accuracy is not good. In this work, we propose a two directional address renaming load value predictor that renames load instruction addresses into a data address and a store instruction address to increase the number of predictable load instructions and improve the prediction accuracy. This method is designed for the current load value predictor. We combine the proposed load value predictor with ALU chaining to improve the superscalar processor performance even more. Experimental results show that the proposed load value predictor improved performance by about 3.54% on its own and by about 5.79% when combined with ALU chaining.

Keywords: load value prediction; ALU chaining; instruction level parallelism; ILP; superscalar processors; data dependence; processor performance.

DOI: 10.1504/IJAMECHS.2014.066926

International Journal of Advanced Mechatronic Systems, 2014 Vol.6 No.1, pp.53 - 64

Received: 04 Aug 2014
Accepted: 24 Sep 2014
Published online: 29 Jan 2015 *

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