Title: Malicious traffic analysis on mobile devices: a hardware solution

Authors: Mario Barbareschi; Antonino Mazzeo; Antonino Vespoli

Addresses: Department of Electrical Engineering and Information Technology, University of Naples 'Federico II', Italy ' Department of Electrical Engineering and Information Technology, University of Naples 'Federico II', Italy ' Department of Electrical Engineering and Information Technology, University of Naples 'Federico II', Italy

Abstract: The security of smartphone devices is increasingly jeopardised by viruses, intrusion attempts and trojans, which most of them come from the internet traffic. Since the involved traffic is huge and has a complex nature, those threats are difficult to discover and immunise. The mobile devices cannot adopt classical approaches to improve security, such as the traffic analysis, because they are mobile, so resource is constrained and without a power supply. As indeed, most widespread mobile operating systems, such as Android, do not provide any software routine to accomplish this analysis. Recently, in the literature, machine learning approaches have been adopted for the traffic analysis and they exploit a hardware implementation to guarantee high packets throughput and low energy consumption. In order to show the feasibility of the approach, in terms of throughput, latency and energy consumption, in this paper we propose a hybrid computing architecture which enables the communication between the Android OS and a traffic analysis hardware accelerator, coexisting on the same chip. At this aim, the proposed architecture is hosted by new FPGA chip family, the Xilinx's Zynq, a SoPC based on dual-core ARM.

Keywords: Android security; field programmable gate array; FPGA; Xilinx Zynq; self-dynamic partial reconfiguration; SDPR; decision tree; hardware accelerator; traffic analysis; mobile devices; big data; malicious traffic; smartphones; internet traffic; machine learning; mobile security; network security; throughput; latency; energy consumption; hybrid computing architecture.

DOI: 10.1504/IJBDI.2015.069093

International Journal of Big Data Intelligence, 2015 Vol.2 No.2, pp.117 - 126

Received: 03 Oct 2014
Accepted: 31 Dec 2014
Published online: 09 May 2015 *

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