Title: Approach to design a high performance fault-tolerant reversible ALU

Authors: Neeraj Kumar Misra; Subodh Wairya; Vinod Kumar Singh

Addresses: Department of Electronics Engineering, Institute of Engineering and Technology, Lucknow, India ' Department of Electronics Engineering, Institute of Engineering and Technology, Lucknow, India ' Department of Electronics Engineering, Institute of Engineering and Technology, Lucknow, India

Abstract: In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of interruption of errors at the outputs. This manuscript focuses the design of ALU in QCA-based and propose new parity preserving gate. It has been introduced that new reversible gate, namely, universal parity preserving gate (UPPG), to optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the simulation result obtained ensures the correctness of the design.

Keywords: reversible logic circuits; parity preserving gates; reversible gates; fault tolerant ALU; ALU design; arithmetic logic unit; quantum cost; garbage output; quantum dot cellular automata; majority voter; quantum computation; fault tolerance; circuit design; simulation.

DOI: 10.1504/IJCAD.2016.075913

International Journal of Circuits and Architecture Design, 2016 Vol.2 No.1, pp.83 - 103

Received: 14 Apr 2015
Accepted: 14 Nov 2015
Published online: 12 Apr 2016 *

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