Article: Effectiveness of body bias and hybrid logic: an energy efficient approach to design adders in sub-threshold regime Journal: International Journal of Circuits and Architecture Design (IJCAD) 2016 Vol.2 No.2 pp.155 - 168 Abstract: Rapid increases in chip complexity, increasingly faster clocks and proliferation of portable devices have combined to make power dissipation an important design parameter. In battery operated digital devices the demand of low power consumption and low energy dissipation in order to maximise battery life are the matter-of-course. Typical energy optimisation measures include voltage scaling and operating at the slowest possible speed. In this paper, to satisfy the low power requirement, sub-threshold logic that involves scaling voltage below the device threshold is being used. The proposed implementation lays emphasis on the usage of hybrid logic with reverse body biasing schemes which reduces high power consumption while giving lesser propagation delay and lesser area in sub-threshold regime. This scheme has been demonstrated on 4-bit, 16-bit and 64-bit carry look-ahead adders and simulated using TSMC 180 nm CMOS technology at 0.4 V supply voltage. Post-layout simulations show significant improvement, exhibiting low power consumption and lesser propagation delay as compared to conventional carry look-ahead adder. Inderscience Publishers - linking academia, business and industry through research

Title: Effectiveness of body bias and hybrid logic: an energy efficient approach to design adders in sub-threshold regime

Authors: Priya Gupta; Ishan Munje; Anu Gupta; Abhijit Asati

Addresses: Department of Electrical and Electronics Engineering, BITS Pilani, Pilani, Rajasthan, 333031, India ' Department of Electrical and Electronics Engineering, BITS Pilani, Pilani, Rajasthan, 333031, India ' Department of Electrical and Electronics Engineering, BITS Pilani, Pilani, Rajasthan, 333031, India ' Department of Electrical and Electronics Engineering, BITS Pilani, Pilani, Rajasthan, 333031, India

Abstract: Rapid increases in chip complexity, increasingly faster clocks and proliferation of portable devices have combined to make power dissipation an important design parameter. In battery operated digital devices the demand of low power consumption and low energy dissipation in order to maximise battery life are the matter-of-course. Typical energy optimisation measures include voltage scaling and operating at the slowest possible speed. In this paper, to satisfy the low power requirement, sub-threshold logic that involves scaling voltage below the device threshold is being used. The proposed implementation lays emphasis on the usage of hybrid logic with reverse body biasing schemes which reduces high power consumption while giving lesser propagation delay and lesser area in sub-threshold regime. This scheme has been demonstrated on 4-bit, 16-bit and 64-bit carry look-ahead adders and simulated using TSMC 180 nm CMOS technology at 0.4 V supply voltage. Post-layout simulations show significant improvement, exhibiting low power consumption and lesser propagation delay as compared to conventional carry look-ahead adder.

Keywords: conventional CMOS; C-CMOS; transmission gates; pass gates; carry look-ahead adder; CLA; reverse body biasing; multiplier accumulator unit; power delay product; pass transistors; sub-threshold regime; hybrid logic; energy efficiency; power dissipation; energy consumption; battery lifetime; simulation; propagation delay.

DOI: 10.1504/IJCAD.2016.082137

International Journal of Circuits and Architecture Design, 2016 Vol.2 No.2, pp.155 - 168

Received: 28 Mar 2015
Accepted: 27 Dec 2015
Published online: 08 Feb 2017 *

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Title: Effectiveness of body bias and hybrid logic: an energy efficient approach to design adders in sub-threshold regime

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