Title: Area efficient SDR receiver without and with dynamic partial reconfiguration

Authors: T. Thammi Reddy; B.K. Madhavi; K. Lal Kishore

Addresses: ECE Department, G. Pulla Reddy College of Engineering (Autonomous), Kurnool Dist. 518007, A.P., India ' ECE Department, Sridevi Women's Engineering College, Hyderabad, 500075, Telangana, India ' Jawaharlal Nehru Technological University (JNTUA), Anantapur, 515002, A.P., India

Abstract: Dynamic partial reconfiguration (DPR) technique is a very efficient for low-cost field programmable gate array (FPGA) for realising several application categories like signal processing. The present work demonstrates a generic framework for implementing Software Defined Radio (SDR) based communication system using DPR. The work switches contexts with two partial reconfiguration blocks. Namely spectrum estimation and frequency shift keying (FSK) receiver blocks. The former uses the streaming type fast Fourier transform (FFT) and later uses frequency shifting and filtering stages. The completely developed FSK receiver is simulated using Modelsim. Xilinx Zynq 7010 SoC with DPR is used for implementation. An FSK signal with symbol rate 64 Kbps is used to drive the analogue to digital converter (ADC) input. The work demonstrates novel direction for SDR implementation with DPR for low-area FPGAs. The results shows 45% lesser FPGA-DSP48 slices are used compared to without-DPR. Reduced power dissipation is observed as by-product.

Keywords: DPR; dynamic partial reconfiguration; FSK generic demodulator; xilinx zynq 7010 soC; DDS; direct digital synthesiser; finite impulse response; FIR filter; Redpitaya.

DOI: 10.1504/IJISTA.2018.091599

International Journal of Intelligent Systems Technologies and Applications, 2018 Vol.17 No.1/2, pp.176 - 194

Received: 23 Mar 2017
Accepted: 27 Aug 2017
Published online: 08 May 2018 *

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