Title: Negative bias temperature instability in strained-Si p-MOSFETs

Authors: Sanghamitra Das; T.P. Dash; Chinmay K. Maiti

Addresses: Department of Electronics and Communication Engineering, Siksha 'O' Anusandhan (Deemed to be University), Bhubaneswar, Odisha, 751030, India ' Department of Electronics and Communication Engineering, Siksha 'O' Anusandhan (Deemed to be University), Bhubaneswar, Odisha, 751030, India ' Department of Electronics and Communication Engineering, Siksha 'O' Anusandhan (Deemed to be University), Bhubaneswar, Odisha, 751030, India

Abstract: Strained-Si p-channel metal oxide semiconductor field effect transistors (MOSFETs) have become the performance boosters beyond 90 nm technology node. Reliability study of these devices is essential as only a few reports are available on this. In this work, we have explored the degradation mechanisms in these devices due to negative bias temperature instability (NBTI). Device simulation results have been calibrated with reported experimental data and a good agreement is observed. The reliability study of these devices has been performed using the two-stage model for defect creation. Study of the drain current degradation and comparison of threshold voltage shift after stressing between the strained-Si and Si channel p-MOSFETs have been performed. The threshold voltage degradation in strained-Si channel p-MOSFETs is found to be considerably higher than that in the bulk-Si devices due to higher fixed oxide charge and interface trap densities at the strained-Si/SiO₂ interface.

Keywords: negative bias temperature instability; NBTI; strained-Si channel p-MOSFET; threshold voltage degradation.

DOI: 10.1504/IJNBM.2018.094911

International Journal of Nano and Biomaterials, 2018 Vol.7 No.4, pp.299 - 310

Received: 02 May 2017
Accepted: 26 Feb 2018
Published online: 26 Sep 2018 *

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