International Journal of High Performance Systems Architecture (4 papers in press)

Regular Issues

• Artificial Intelligence for Energy and QoS-Aware Proactive Dynamic Virtual Machines Consolidation in Cloud-Edge Data Centres  
  by Marwan Mbarek, Abdelkarim Ait Temghart, Mohamed Lazaar 
  Abstract: By minimizing the number of active servers, virtual machine consolidation (VMC) is a strategy for reducing electricity consumption while maintaining service level agreements (SLAs). However, future resource demands have not been considered by current VMC algorithms, which primarily concentrate on the requirements of all virtual machines (VMs) operating in a data center. Furthermore, the majority of the existing works ignore the security risks associated with VM placement. Therefore, we suggest using recurrent neural networks (RNNs) for capacity planning and multi-objective optimization for SLA constraints. Initially, the trade-off between the competing objectives of power, performance, and security is evaluated using a multi-objective particle swarm optimization (MOPSO) technique. Secondly, we provide a novel method for workload prediction based on gated recurrent units optimized by genetic algorithm (GA-GRU). Overall, the findings show that the suggested framework, which takes energy savings and QoS guarantees into account, leads to the optimal design of data centers.
  Keywords: cloud computing; edge computing; data centers; VM consolidation; VM placement; workload prediction; PSO; GRU; GA; MOPSO; energy; security; SLA; QoS.
  DOI: 10.1504/IJHPSA.2024.10067941
   
  
• HW/SW Co-Design of Scalar Multiplication Based on the Affine Coordinates System  
  by Mohamed Issad 
  Abstract: Scalar Multiplication (SM) is the kernel computation in modern public key cryptography based on elliptic curves. This paper presents the implementation of the SM using affine coordinates system, over a prime field Fp. The target design is a System-on-Chip, based on Hardware/Software Zynq platform. In SM algorithm, the coordinates computations of points require basic arithmetic operations in Fp. Among these operations, Modular Inversion (MI) and Modular Multiplication (MM) are complex, because they require the computation of the division. In order to enhance the trade-off: execution time, occupied area, flexibility and configurability, we propose an embedded system where the MI and the MM are implemented around the Zynq Processing System (PS), as accelerator cores. The control of the SM algorithm, the modular addition and subtraction are performed in PS. The implementation results show that the execution times of 256-bit and 521-bit SM computations are 28 ms and 151.4 ms, respectively.
  Keywords: Elliptic Curve Cryptography; Scalar Multiplication; Modular Arithmetic; FPGA; Zynq.
  DOI: 10.1504/IJHPSA.2024.10068087
   
  
• Flexible and Area-optimised Hardware Architectures of LEA Block Cipher for IoT Applications  
  by Chaitanya Kella, Zeesha Mishra, Pulkit Singh, Bibhudendra Acharya 
  Abstract: Information security and privacy are indispensable aspects of IoT and cyberphysical system technologies as sensitive data is being transmitted in many applications. They are restricted in terms of resources like memory, computing power, etc. Lightweight cryptography delivers solutions by providing sufficient security and using minimal resources. Many lightweight ciphers have been proposed over the years for a variety of applications. This paper proposes three flexible and area-optimized LEA block cipher hardware architectures that guarantee appropriate speed and security. These flexible serial architectures are designed to handle all three key sizes of LEA cipher i.e., 128, 192, and 256 bits. The proposed architectures are implemented at the RTL level using Verilog in Xilinx ISE on different families of FPGA devices. The proposed architectures are designed to render better throughput rates at much lesser areas.
  Keywords: Lightweight cryptography; IoT; LEA block cipher; Flexible architecture; Throughput; FPGA.
  DOI: 10.1504/IJHPSA.2024.10068591
   
  
• Performance Optimised Architectures of Lightweight HIGHT Cipher for Low-Resource IoT Applications  
  by Gandu Ramu, Zeesha Mishra, Pulkit Singh, Bibhudendra Acharya 
  Abstract: A major concern in many data-sensitive applications of Internet of Things (IoT) platforms is security and privacy. The execution-speed, ability to adapt, and processing capacity of IoT systems are limited. Various encryption techniques have been proposed recently to ensure the security of IoTs communication. In this paper, different architectures of HIGHT cipher are implemented on the different family of FPGAs, in which round-based has a smaller number of flip-flops, high-speed architecture has good throughput. In addition, serial RAM-based design has low power consumption and low area consumption of 0.572 W and 34, respectively. Moreover, combined encryption/decryption architecture consumes resources of flip-flop 197, slices of 151, LUTs of 502, and frequency of 249MHz.The percentage improvement in the area over the previous work is around 135% and 97% in maximum operating frequency, respectively. The results of hardware design are thoroughly evaluated and compared to the most relevant lightweight block ciphers.
  Keywords: Lightweight cryptography; Block ciphers; FPGA; ARX operations; Feistel structures.
  DOI: 10.1504/IJHPSA.2025.10070161