A design methodology for mobile and embedded applications on FPGA-based dynamic reconfigurable hardware
by Darshika G. Perera; Kin Fun Li
International Journal of Embedded Systems (IJES), Vol. 11, No. 5, 2019

Abstract: With the proliferation of mobile/embedded devices, multiple running applications are becoming a necessity on these devices. Thus, state-of-the-art techniques are needed to support complex applications running on mobile systems. We envision in the near future, many mobile devices will be implemented/delivered on FPGA-based reconfigurable chips. Previous analysis illustrated that FPGA-based dynamic-reconfigurable-hardware is currently the best option to deliver embedded applications that have stringent requirements. However, computation models and application characteristics play significant roles in determining whether this hardware is indeed a good match for specific embedded applications. Furthermore, selecting a specific dynamic reconfiguration method (out of many) and designing the corresponding hardware architectures for an application are important and challenging tasks. This paper proposes a design methodology for FPGA-based dynamic-reconfigurable-hardware that provides guidelines in mapping application's computation models and characteristics to the most suitable reconfiguration methods. Pipelined and functional-parallel models are used as case studies to illustrate the design methodology.

Online publication date: Tue, 24-Sep-2019

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