Reconfigurable half-precision floating-point real/complex fused multiply and add unit
by J. Jean Jenifer Nesam; S. Sivanantham
International Journal of Materials and Product Technology (IJMPT), Vol. 60, No. 1, 2020

Abstract: Multiplication followed by an addition/subtraction is the common operation in many digital signal and image processing applications. This paper presents a reconfigurable floating-point real/complex fused multiply and add (R/C-FMA) unit using small precision (IEEE-754-2008 16-bit half-precision) format. The developed FMA can be reconfigurable from real to complex based on the control bits. This architecture performs real FMA [(a × b) + c], complex FMA {[(a + ib) × (c + id)] + (e + if)} or mixed real and complex FMA {[(a + ib) × (c + id)] + e}. The field programmable gate array (FPGA) implementation of R/C-FMA design, utilises the modern features of inbuilt DSP blocks for mantissa multiplication and addition/subtraction. The efficient DSP usage for fp16 FMA design shows a 60% reduction in LUT area when compared to conventional fp32 FMA.

Online publication date: Tue, 14-Jul-2020

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

 
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Materials and Product Technology (IJMPT):
Login with your Inderscience username and password:

Username:        Password:          Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com