Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs Online publication date: Fri, 26-Jun-2009
by Daniel Ziener, Jurgen Teich
International Journal of Autonomous and Adaptive Communications Systems (IJAACS), Vol. 2, No. 3, 2009
Abstract: In this paper, we introduce new concepts and methods for checking the correctness of control flow instructions (CFI) issued during the execution of programs for embedded RISC CPUs. Our proposed methodology is able to detect at run-time any error of illegal or faulty direct jump and branch instruction as well as call and return form subroutine for a given program code. Furthermore, two different hardware concepts and implementations of generic control flow (CF) checker units which may be tightly attached to a given CPU are proposed. These implementations can detect and even avoid the execution of faulty CFI at very low area and usually no latency penalty. Other benefits of this novel approach are that the application code must not be changed or augmented by signatures or additional instructions at all. The presented approach is, thus, completely transparent to the program developer.
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