A new design leads to efficient bit-serial FPGA implementation for the biorthogonal 5/3 DWT filter bank
by Jassim M. Abdul-Jabbar; Ahmed M. Alkababji; Dhafir A. Alneema
International Journal of Reasoning-based Intelligent Systems (IJRIS), Vol. 4, No. 4, 2012

Abstract: In this paper, an efficient design of the lattice structure of the biorthogonal 5/3 discrete wavelet filter bank is introduced and then implemented using the technique of bit-serial implementation. This technique is usually used when area has a significant importance for the designer, where it is possible to be used for the designs that consist of similar parts of processing elements. Using VHDL language, the FPGA Spartan-3E device is exploited for implementing the designed structure. The implementation complexity (utilised chip area) of the resulting structures is significantly reduced as compared with the pipelined implementation of the same design. It also outperforms another efficient implementation of the same filter bank using lifting scheme.

Online publication date: Sun, 27-Jan-2013

The full text of this article is only available to individual subscribers or to users at subscribing institutions.

 
Existing subscribers:
Go to Inderscience Online Journals to access the Full Text of this article.

Pay per view:
If you are not a subscriber and you just want to read the full contents of this article, buy online access here.

Complimentary Subscribers, Editors or Members of the Editorial Board of the International Journal of Reasoning-based Intelligent Systems (IJRIS):
Login with your Inderscience username and password:

Username:        Password:          Forgotten your password?

Want to subscribe?
A subscription gives you complete access to all articles in the current issue, as well as to all articles in the previous three years (where applicable). See our Orders page to subscribe.

If you still need assistance, please email subs@inderscience.com